Group Members
Projects
Survey of DRAM
The growing performance gap between the processor and memory has accelerated the development of many interesting Dynamic Random Access memory(DRAM) architectures from the memory manufacturers. However, to the best of our knowledge, there has been no recent comprehensive survey of DRAM operations, technology and architectures. Most of the surveys on DRAM are either too old to cover more recent architectures, or are intended for DRAM users to choose the right memory for their system. This project intends to fill that gap by providing a comprehensive survey of DRAM operations, and various new DRAM architectures from a computer system designer's point of view.
Extending In-Memoy BIST Logic for IRAM
The growing gap between processor and memory performance results in increasing demand of memory bandwidth. The DRAM memory core offers a tremedous amount of on-chip bandwidth which can not be utilized because of memory chip pin limitations. In this project, we explore the idea of using on-chip memory testing logic, called Built-In-Self-Test (BIST) to exploit this bandwidth and provide efficient in-memory implementation of memory block copy and clear operations. In addition, we use the memory block copy operation as a primitive to improve the PCI bandwidth for scatter/gather operation. We also perform an extensive survey of existing DRAM memory technologies to provide background information.
Publications
Dynamic Random Access Memory: A Survey (postscript paper)
Tulika Mitra
Research Proficiency Examination Report, February 1999
(Talk slides from RPE presentation)
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